Directed Audio 6550 Service Manual download pdf (Page 25)

Main Board

Electronic Theory of Operation

Rev. 01 Model 515B/C

Service Manual

The CS5503 converter continuously samples its input, converts the value to a digital word, puts

the word in its output buffer (overwriting previous buffer contents), then repeats the process by

again sampling its input. The frequency of the sample/convert/overwrite-buffer sequence is

based on the 3.2768 MHz clock signal at the ADC pin 3 (ADCCLK) input.

The microprocessor starts a read cycle of the Infrared channel by bringing IC23 pin 16

(ADCIRCS*) low. A Red channel read starts when IC24 pin 16 (ADCREDCS*) is brought low.

On the falling edge of the ADC’s CS*

, the output word’s MSB (most significant bit) appears at

the pin-20 SDATA (Serial Data) output. The SDATA line connects directly to the

microprocessor’s serial input (RXS) pin. The remaining bits (in descending order) are output

from SDATA with subsequent falling edges of the Serial Clock (SCLK) input at pin 19. The

SDATA output automatically goes to a 3-state (high impedance) condition after completing a

word transmission, thus freeing the data line for other uses (i.e., the other ADC channel).

The Serial Clock rate is significantly slower than the ADC sampling rate. As a result, the ADC

rewrites its output buffer with new information at a faster rate than the data can be read from the

buffer. No conflict occurs, however, because while CS*

is low (during the read cycle), the ADC

does not update its output buffer—the current word is not overwritten. After the processor

receives the entire word, it allows the convertor’s CS*

to return high, and the ADC resumes its

sample/convert/overwrite-buffer cycle.

5.2.7

Sensor Status Decoding and Conversion

The microprocessor monitors several sensor parameters in addition to the Red and Infrared data

channels. It monitors the status parameters, as well as the voltage of the monitor’s internal

battery. See page 3 on schematic.

The 8-to-1 multiplexer, IC25, decodes the A0MUX-A2MUX input address lines and connects

one of eight status parameter inputs to the multiplexer output at IC25 pin 3. Resistor R88 and

diode D19 prevent negative voltages from reaching the input to the analog-to-digital converter,

IC26.

IC26 is an 8-bit analog-to-digital convertor with a serial data output. While the IC26 Chip Select

(ADC3CS*

) input is high, the CLK input and SDATA output are in 3-state mode. When CS is

brought low (under processor control), the most significant bit (D7) of the PREVIOUS data

conversion becomes available at the SDATA pin. The remaining bits (D6-D0) are shifted out on

subsequent falling edges of the CLK input. On the clock pulse following the one that shifts out

the least significant bit (D0), the CLK and SDATA lines are returned to 3-state and the ADC

performs a new conversion based on the input it receives from the IC25 channel selected by the

A0MUX-A2MUX input address lines.

The ADC sample/convert/store-result cycle is based on internal chip timing and not the CLK

input which (along with CS

) only controls serial data output. Thus the CS line is free to return

high once the ADC cycle begins.

5.2.8

Front End Timing Signals

See page 1 on schematic. A 14 stage divider IC6, acts as a timing sequencer. The ADCCLK

input is the clock input, the RESET line is the clear input, used for clearing the chip at power

up. The Q4-Q11 outputs of IC6 are divided down from the clock input and feed IC13, the data

sampling controller. The Q14 output of IC6 is used as an interrupt that is generated every 5

milliseconds (INT5MS).

The data sampling controller IC13 is a Programmable Electrically Erasable Logic device

(PEEL). The PEEL uses the outputs from IC6 and generates the front end timing signals. These

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 73 74

Comments to this Manuals

No comments

Directed Audio 6550 Service Manual Page 25

Comments to this Manuals